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1 edi2ag27265v white electronic designs corporation ? westborough, ma 01581 ? (508) 366-5151 www.whiteedc.com july 1 9 99 rev eco 1 megabyte sync/sync burst, small outline dimm features pin names the edi2ag27265vxxd1 is a synchronous/synchronous burst sram, 72 position 30 dimm(144 contacts) module, organized as 2x64kx72. the module contains four (4) synchronous burst ram devices, packaged in the industry standard jedec 14mmx20mm tqfp placed on a multilayer fr4 substrate. the module architecture is defined as a sync/sync burst, flow-through, with support for either linear or sequential burst. this module provides high performance, 2-1-1-1 accesses when used in burst mode, and used as a synchronous only mode, provides a high performance cost advantage over bicmos aysnchronous device architectures. synchronous only operations are performed via strapping adsc\ low, and adsp\ / adv\ high, which provides for ultra fast accesses in read mode while providing for internally self-timed early writes. synchronous/synchronous burst operations are in relation to an externally supplied clock, registered address, registered global write, registered enables as well as an asynchronous output enable. this module has been defined with full flexibility, which allows individual control of each of the eight bytes, as well as quad words in both read and write operations. ? 2x64kx72 synchronous, synchronous burst ? flow-through architecture ? sequential burst mode ? clock controlled registered bank enables (e1\, e2) ? clock controlled byte write mode enable (bwe\) ? clock controlled byte write enables (bw1\ - bw8\) ? clock controlled registered address ? clock controlled registered global write (gw\) ? aysnchronous output enable (g\) ? internally self-timed write ? gold lead finish ? 3.3v + 10% operation ? access speed(s): tkhqv=8.5, 9, 10, 12ns ? common data i/o ? high capacitance (30pf) drive, at rated access speed ? single total array clock ? multiple vcc and gnd dq0-dq63 input/output bus dqp0-dqp7 parity bits a0-a15 address bus e1\, e2 synchronous bank enables bwe\ byte write mode enable bw1\-bw8\ byte write enables clk array clock gw\ synchronous global write enable g\ asynchronous output enable vcc 3.3v power supply vss gnd
2 white electronic designs corporation ? westborough, ma 01581 ? (508) 366-5151 www.whiteedc.com edi2ag27265v july 1 9 99 rev eco pin configuration
3 edi2ag27265v white electronic designs corporation ? westborough, ma 01581 ? (508) 366-5151 www.whiteedc.com july 1 9 99 rev eco functional block diagram
4 white electronic designs corporation ? westborough, ma 01581 ? (508) 366-5151 www.whiteedc.com edi2ag27265v july 1 9 99 rev eco pin descriptions dimm pins symbol type description 3, 6, 7, 10, 11 a0-a17 input addresses: these inputs are registered and must meet the setup and hold 14, 15, 18, 19, 20 synchronous times around the rising edge of clk. the burst counter generates internal 17, 16, 13, 12, 98 addresses associated with a0 and a1, during burst and wait cycle. 33, 47, 61 bw1\, bw2\, input byte write: a byte write is low for a write cycle and high for a read 75, 89, 103 bw3\, bw4\, synchronous cycle. bw0/ controls dq0-7 and dqp0, bw1\ controls dq8-15 and dqp1. 117, 13 bw5\, bw6\, bw2\ controls dq16-23 and dqp2. bw3\ controls dq24-31 and dqp3. bw7\, bw8\ bw4\ controls dq32-39 and dqp4. bw5\ controls dq40-47 and dqp5. bw6\ controls dq48-55 and dqp6. bw7\ controls dq56-64 and dqp7. 32 bwe\ input write enable: this active low input gates byte write operations and must synchronous meet the setup and hold times around the rising edge of clk. 25 gw\ input global write: this active low input allows a full 72-bit write to occur synchronous independent of the bwe\ and bwx\ lines and must meet the setup and hold times around the rising edge of clk. 30 clk input clock: this signal registers the addresses, data, chip enables, write control synchronous and burst control inputs on its rising edge. all synchronous inputs must meet setup and hold times around the clock?s rising edge. 29, 31, e1\, e2\ input bank enables: these active low inputs are used to enable each e3\, e4\ synchronous individual bank and to gate adsp\. 23 g\ input output enable: this active low asynchronous input enables the data output drivers. 26 adv\ input address status processor: this active low input is used to control the synchronous internal burst counter. a high on this pin generates wait cycle (no address advance). 27 adsp\ input address status processor: this active low input, along with el\ and eh\ synchronous being low, causes a new external address to be registered and a read cycle is initiated using the new address. 28 adsc\ input address status controller: this active low input causes device to be de- synchronous selected or selected along with new external address to be registered. a read or write cycle is initiated depending upon write control inputs. various dq0-63 input/output data inputs/outputs: first byte is dq0-7, second byte is dq8-15, third byte is dq16-23, fourth byte is dq24-31, fifth byte is dq32-39, sixth byte is dq40-47, seventh byte is dq48-55 and the eight byte is dq56-64. 38, 48, 62 dqp0-7 input/output parity inputs/outputs: dqp0 is parity bit for dq0-7. dqp1 is parity bit for dq8-15. 76, 90, 104 dqp2 is parity bit for dq16-23. dqp3 is parity bit for dq24-31. dqp4\ is parity 118, 132 bit for dq32-39. dqp5 is parity bit for dq40-47. dqp6\ is parity bit for dq48-55. dqp7 is parity bit for dq56-64 and dqp7.in order to use the device configured as a128k x 64, the parity bits need to be tied to vss through a 10k ohm resistor. various vcc supply core power supply: +3.3v -5%/+10% various vss ground ground
5 edi2ag27265v white electronic designs corporation ? westborough, ma 01581 ? (508) 366-5151 www.whiteedc.com july 1 9 99 rev eco synchronous burst - truth table operation e1\ e2\ adsp\ adsc\ adv\ gw\ g\ clk dq addr. used deselected cycle, power down; bank 1 h x x l x x x l-h high-z none deselected cycle, power down; bank 2 x h x l x x x l-h high-z none read cycle, begin burst; bank 1 l h l x x x l l-h q external read cycle, begin burst; bank 1 l h l x x x h l-h high-z external read cycle, begin burst; bank 2 h l l x x x l l-h q external read cycle, begin burst; bank 2 h l l x x x h l-h high-z external write cycle, begin burst; bank 1 l h h l x l x l-h d external write cycle, begin burst; bank 2 h l h l x l x l-h d external read cycle, begin burst; bank 1 l h h l x h l l-h q external read cycle, begin burst; bank 1 l h h l x h h l-h high-z external read cycle, begin burst; bank 2 h l h l x h l l-h q external read cycle, begin burst; bank 2 h l h l x h h l-h high-z external read cycle, continue burst; bank 1 x h x h l h l l-h q next read cycle, continue burst; bank 1 x h x h l h h l-h high-z next read cycle, continue burst; bank 2 h x x h l h l l-h q next read cycle, continue burst; bank 2 h x x h l h h l-h high-z next read cycle, continue burst; bank 1 h h x h l h l l-h q next read cycle, continue burst; bank 1 h h x h l h h l-h high-z next read cycle, continue burst; bank 2 h h x h l h l l-h q next read cycle, continue burst; bank 2 h h x h l h h l-h high-z next write cycle, continue burst; bank 1 x h h h l l x l-h d next write cycle, continue burst; bank 1 h h x h l l x l-h d next write cycle, continue burst; bank 2 h x h h l l x l-h d next write cycle, continue burst; bank 2 h h x h l l x l-h d next read cycle, suspend burst; bank 1 x h h h h h l l-h q current read cycle, suspend burst; bank 1 x h h h h h h l-h high-z current read cycle, suspend burst; bank 2 h x h h h h l l-h q current read cycle, suspend burst; bank 2 h x h h h h h l-h high-z current read cycle, suspend burst; bank 1 h h x h h h l l-h q current read cycle, suspend burst; bank 1 h h x h h h h l-h high-z current read cycle, suspend burst; bank 2 h h x h h h l l-h q current read cycle, suspend burst; bank 2 h h x h h h h l-h high-z current write cycle, suspend burst; bank 1 x h h h h l x l-h d current write cycle, suspend burst; bank 1 h h x h h l x l-h d current write cycle, suspend burst; bank 2 h x h h h l x l-h d current write cycle, suspend burst; bank 2 h h x h h l x l-h d current
6 white electronic designs corporation ? westborough, ma 01581 ? (508) 366-5151 www.whiteedc.com edi2ag27265v july 1 9 99 rev eco dc electrical characteristics - read cycle recommended dc operating conditions absolute maximum ratings* ac test conditions ac test load synchronous only - truth table max description sym typ 8.5 5 10 12 units power supply current icc1 1.35 1.2 1.1 1.1 1.0 a power supply current icc .700 .550 .800 .750 .700 a device selected,no operation cmos standby icc3 200 300 300 300 300 ma clock running-deselect icck 500 750 750 750 750 ma parameter sym min typ max units supply voltage vcc 3.14 3.3 3.6 v supply voltage vss 0.0 0.0 0.0 v input high vih 1.1 3.0 vcc+0.3 v input low vil -0.3 0.0 0.3 v input leakage ili -2 1 2 m a output leakage ilo -2 1 2 m a *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in operational sections of this specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. voltage on vcc relative to vss -0.5v to +4.6v vin -0.5v to vcc +0.5v storage temperature -55c to +125c operating temperature (commercial) 0c to +70c operating temperature (industrial) -40c to +85c short circuit output current 10 ma operation e1\ e2\ gw\ g\ zz clk dq synchronous write-bank 1 l h l h l high-z synchronous read-bank 1 l h h l l synchronous write-bank 2 h l l h l high-z synchronous read-bank 2 h l h l l input pulse levels vss to 3.0v input and output timing ref. 1.25v output test equivalencies dq z 0 = 50 w fig. 1 output load equivalent vt = 1.25v 50 w
7 edi2ag27265v white electronic designs corporation ? westborough, ma 01581 ? (508) 366-5151 www.whiteedc.com july 1 9 99 rev eco read cycle timing parameters b urst address table (mode=gnd) b urst address table (mode=nc/vcc) synchronous only read cycle first second third fourth address address address address (external) (internal) (internal) (internal) a..a00 a..a01 a..a10 a..a11 a..a01 a..a00 a..a11 a..a10 a..a10 a..a11 a..a00 a..a01 a..a11 a..a10 a..a01 a..a00 8.5ns 9ns 10ns 12ns description sym min max min max min max min max units clock cycle time tkhkh * * 10 10 15 ns clock high time tkhkl * * 4 5 5 ns clock low time tklkh * * 9 5 5 ns clock to output valid tkhqv * * 9 10 12 ns clock to output invalid tkhqx1 * * 3 3 3 ns clock to output low-z tkhqx * * 2 2 2 ns output enable to output valid tglqv * * 4 4 5 ns output enable to output low-z tglqx * * 0 0 0 ns output enable to output high-z tghqz * * 9 9 5 ns address setup tavkh * * 2.5 2.5 2.5 ns bank enable setup tevkh * * 2.5 2.5 2.5 ns address hold tkhax * * 1.0 1.0 1.0 ns bank enable hold tkhex * * 1.0 1.0 1.0 ns first second third fourth address address address address (external) (internal) (internal) (internal) a..a00 a..a01 a..a10 a..a11 a..a01 a..a10 a..a11 a..a00 a..a10 a..a11 a..a00 a..a01 a..a11 a..a00 a..a01 a..a10 *tbd *tbd ex\ g\
8 white electronic designs corporation ? westborough, ma 01581 ? (508) 366-5151 www.whiteedc.com edi2ag27265v july 1 9 99 rev eco write cycle timing parameters sync-burst read cycle 8.5ns 9ns 10ns 12ns description sym min max min max min max min max units clock cycle time tkhkh 10 12 15 ns clock high time tkhkl 4 5 5 ns clock low time tklkh 4 5 5 ns address setup tavkh 2.5 2.5 2.5 ns address hold tkhax 1.0 1.0 1.0 ns bank enable setup tevkh 2.5 2.5 2.5 ns bank enable hold tkhex 1.0 1.0 1.0 ns global write enable setup twvkh 2.5 2.5 2.5 ns global write enable hold tkhwx 1.0 1.0 1.0 ns data setup tdvkh 2.5 2.5 2.5 ns data hold tkhdx 1.0 1.0 1.0 ns ex\ g\
9 edi2ag27265v white electronic designs corporation ? westborough, ma 01581 ? (508) 366-5151 www.whiteedc.com july 1 9 99 rev eco sync (non-burst) write cycle syncburst write cycle g\ ex\ ex\
10 white electronic designs corporation ? westborough, ma 01581 ? (508) 366-5151 www.whiteedc.com edi2ag27265v july 1 9 99 rev eco sync (non-burst) read/write cycle
11 edi2ag27265v white electronic designs corporation ? westborough, ma 01581 ? (508) 366-5151 www.whiteedc.com july 1 9 99 rev eco package description ordering information part number organization voltage speed (ns) package edi2ag27265v85d1* 2x64kx72 3.3 8.5 144 so-dimm edi2ag27265v9d1* 2x64kx72 3.3 9 144 so-dimm EDI2AG27265V10D1 2x64kx72 3.3 10 144 so-dimm edi2ag27265v12d1 2x64kx72 3.3 12 144 so-dimm *consult factory for availability package no. 409 144 lead so-dimm

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